1. Field of the Invention
The present invention relates to a current command type PWM (Pulse Width Modulation) inverter apparatus, in particular, to a current command type PWM inverter apparatus for driving and controlling a three-phase motor based on periodical state updating timings.
2. Description of the Prior Art
In recent years, current command type PWM inverters are extensively used in driving and controlling three-phase motors such as induction motors, synchronous motors, reluctance motors, or the like.
In comparison with a voltage command type PWM inverter which commands a voltage to be applied to a motor and applies the voltage conforming to the command, to the motor, the current command type PWM inverter, which commands a current to be flowed into a motor and compulsorily flows the current conforming to the command through the motor, is advantageous in responsibility and controllability. In particular, for controlling an AC servomotor and the like, the current command type PWM inverter is adopted in almost all the cases.
A construction of a generic current command type PWM inverter system will be described here with reference to FIG. 9.
Referring to FIG. 9, first of all, a fundamental frequency f and an effective current value ip of a three-phase AC (Alternating Current) current waveform to be supplied to a three-phase motor 1 are set in a current command generator circuit 7, and based on these information, the current command generator circuit 7 internally generates line current command signals to be flowed into the three-phase motor 1 as a first line current command signal iTU, a second line current command signal iTV and a third line current command signal iTW.
Then, a motor current detector circuit 9 detects two line currents of the three-phase motor 1, obtains the remaining one line current by obtaining the sum of the detected two line currents and inverting the sign of the sum value, and outputs the resulting detected currents as a first detected line current iFU, a second detected line current iFV and a third detected line current iFW. It is to be noted that the motor current detector circuit 9 may detect the three line currents of the three-phase motor 1, and then output the first detected line current iFU, the second detected line current iFV and the third detected line current iFW.
Then, a current controller 106 receives the first line current command signal iTU, the second line current command signal iTV, the third line current command signal iTW, the first detected line current iFU, the second detected line current iFV and the third detected line current iFW, and generates a first switching command signal PU, a second switching command signal PV and a third switching command signal PW so that the first line current command signal iTU, the second line current command signal iTV and the third line current command signal iTW are made to respectively coincide with the first detected line current iFU, the second detected line current iFV and the third detected line current iFW as far as possible.
Further, a main circuit power controller 8 comprises:
(a) a main circuit DC (Direct Current) power source 3; and PA1 (b) a main circuit power device circuit 2 having a three-phase bridge connection, wherein the main circuit power device circuit 2 comprises: PA1 motor current detecting means for directly or indirectly detecting line currents flowing from respective lines of said PWM inverter apparatus into a three-phase motor and outputting a first detected line current, a second detected line current and a third detected line current; PA1 current command generating means for generating and outputting a first line current command signal, a second line current command signal and a third line current command signal for commanding the line currents to be flowed from said respective lines into the three-phase motor; PA1 first comparing means for comparing the first line current command signal with the first detected line current, outputting a first line current comparison signal having zero level when a difference between the first line current command signal and the first detected line current falls within an allowance range including zero, outputting the first line current command signal having a first level when the difference between the first line current command signal and the first detected line current falls outside the allowance range and when the first detected line current is equal to or greater than the first line current command signal, and outputting the first line current comparison signal having a second level when the difference between the first line current command signal and the first detected line current falls outside the allowance range and when the first detected line current is smaller than the first line current command signal; PA1 second comparing means for comparing the second line current command signal with the second detected line current, outputting a second line current comparison signal having zero level when a difference between the second line current command signal and the second detected line current falls within an allowance range including zero, outputting the second line current comparison signal having a first level when the difference between the second line current command signal and the second detected line current falls outside the allowance range and when the second detected line current is equal to or greater than the second line current command signal, and outputting the second line current comparison signal having a second level when the difference between the second line current command signal and the second detected line current falls outside the allowance range and when the second detected line current is smaller than the second line current command signal; PA1 third comparing means for comparing the third line current command signal with the third detected line current, outputting a third line current comparison signal having zero level when a difference between the third line current command signal and the third detected line current falls within an allowance range including zero, outputting the third line current comparison signal having a first level when the difference between the third line current command signal and the third detected line current falls outside the allowance range and when the third detected line current is equal to or greater than the third line current command signal, and outputting the third line current comparison signal having a second level when the difference between the third line current command signal and the third detected line current falls outside the allowance range and moreover the third detected line current is smaller than the third line current command signal; PA1 a main circuit DC power source; PA1 main circuit power device circuit having a three-phase bridge connection and comprising: PA1 until the next state updating first timing, said logic circuit generates and outputs either one group of the first, second and third switching command signals or the fourth, fifth and sixth switching command signals for respectively turning off the first, second and third main circuit switching power devices or the fourth, fifth and sixth main circuit switching power devices, and further generates and outputs the remaining group of the switching command signals for respectively turning on the remaining group of the main circuit switching power devices. PA1 said logic circuit maintains the on-state or off-state of the main circuit switching power devices obtained just before the state updating first timing, until the next state updating first timing. PA1 for a time interval from a second timing when the first line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the first switching command signal for turning off the first main circuit switching power device and further generates and outputs the fourth switching command signal for turning on the fourth main circuit switching power device, PA1 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the first level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the first, third and fifth switching command signals for respectively turning off the first, third and fifth main circuit switching power devices, and further generates and outputs the second, fourth and sixth switching command signals for respectively turning on the second, fourth and sixth main circuit switching power devices, and PA1 for a time interval from a second timing when the first line current comparison signal changes from the second level to the first level to the next state updating first timing, said logic circuit generates and outputs the second switching command signal for turning off the second main circuit switching power device and further generates and outputs the fifth switching command signal for turning on the fifth main circuit switching power device, PA1 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the second level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the first, second and sixth switching command signals for respectively turning off the first, second and sixth main circuit switching power devices, and further generates and outputs the third, fourth and fifth switching command signals for respectively turning on the third, fourth and fifth main circuit switching power devices, and PA1 for a time interval from a second timing when the third line current comparison signal changes from the second level to the first level to the next state updating first timing, said logic circuit generates and outputs the third switching command signal for turning off the third main circuit switching power device and further generates and outputs the sixth switching command signal for turning on the sixth main circuit switching power device, PA1 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the first level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the first, fifth and sixth switching command signals for respectively turning off the first, fifth and sixth main circuit switching power devices, and further generates and outputs the second, third and fourth switching command signals for respectively turning on the second, third and fourth main circuit switching power devices, and PA1 for a time interval from a second timing when the first line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and further generates and outputs the first switching command signal for turning on the first main circuit switching power device, PA1 wherein, when the first line current comparison signal has the first level, the second line current comparison signal has the second level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the second, fourth and sixth switching command signals for respectively turning off the second, fourth and sixth main circuit switching power devices, and further generates and outputs the first, third and fifth switching command signals for respectively turning on the first, third and fifth main circuit switching power devices, and PA1 for a time interval from a second timing when the second line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and further generates and outputs the second switching command signal for turning on the second main circuit switching power device, and PA1 wherein, when the first line current comparison signal has the first level, the second line current comparison signal has the first level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the third, fourth and fifth switching command signals for respectively turning off the third, fourth and fifth main circuit switching power devices, and further generates and outputs the first, second and sixth switching command signals for respectively turning on the first, second and sixth main circuit switching power devices, and PA1 for a time interval from a second timing when the third line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the sixth switching command signal for turning off the sixth main circuit switching power device and further generates and outputs the third switching command signal for turning on the third main circuit switching power device. PA1 for a time interval from a second timing when the first line current comparison signal changes to the zero level to the next state updating first timing, said logic circuit generates and outputs the first switching command signal for turning off the first main circuit switching power device and further generates and outputs the fourth switching command signal for turning on the fourth main circuit switching power device, PA1 wherein, when the first line current comparison signal has the zero level, the second line current comparison signal has the second level and the third line current comparison signal has the zero level at the state updating first timing, said logic circuit generates and outputs the first, third and fifth switching command signals for respectively turning off the first, third and fifth main circuit switching power devices, and further generates and outputs the second, fourth and sixth switching command signals for respectively turning on the second, fourth and sixth main circuit switching power devices, and PA1 for a time interval from a second timing when the second line current comparison signal changes to the zero level to the next state updating first timing, said logic circuit generates and outputs the second switching command signal for turning off the second main circuit switching power device and further generates and outputs the fifth switching command signal for turning on the fifth main circuit switching power device, PA1 wherein, when the first line current comparison signal has the zero level, the second line current comparison signal has the zero level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the first, second and sixth switching command signals for respectively turning off the first, second and sixth main circuit switching power devices, and further generates and outputs the third, fourth and fifth switching command signals for respectively turning on the third, fourth and fifth main circuit switching power devices, and PA1 for a time interval from a second timing when the third line current comparison signal changes to the zero level to the next state updating first timing, said logic circuit generates and outputs the third switching command signal for turning off the third main circuit switching power device and further generates and outputs the sixth switching command signal for turning on the sixth main circuit switching power device, PA1 wherein, when the first line current comparison signal has the first level, the second line current comparison signal has the zero level and the third line current comparison signal has the zero level at the state updating first timing, said logic circuit generates and outputs the first, fifth and sixth switching command signals for respectively turning off the first, fifth and sixth main circuit switching power devices, and further generates and outputs the second, third and fourth switching command signals for respectively turning on the second, third and fourth main circuit switching power devices, and PA1 for a time interval from a second timing when the first line current comparison signal changes to the zero level to the next state updating first timing, said logic circuit generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and further generates and outputs the first switching command signal for turning on the first main circuit switching power device, PA1 wherein, when the first line current comparison signal has the zero level, the second line current comparison signal has the first level and the third line current comparison signal has the zero level at the state updating first timing, said logic circuit generates and outputs the second, fourth and sixth switching command signals for respectively turning off the second, fourth and sixth main circuit switching power devices, and further generates and outputs the first, third and fifth switching command signals for respectively turning on the first, third and fifth main circuit switching power devices, and PA1 for a time interval from a second timing when the second line current comparison signal changes to the zero level to the next state updating first timing, said logic circuit generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and further generates and outputs the second switching command signal for turning on the second main circuit switching power device, and PA1 wherein, when the first line current comparison signal has the zero level, the second line current comparison signal has the zero level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the third, fourth and fifth switching command signals for respectively turning off the third, fourth and fifth main circuit switching power devices, and further generates and outputs the first, second and sixth switching command signals for respectively turning on the first, second and sixth main circuit switching power devices, and PA1 for a time interval from a second timing when the third line current comparison signal changes to the zero level to the next state updating first timing, said logic circuit generates and outputs the sixth switching command signal for turning off the sixth main circuit switching power device and further generates and outputs the third switching command signal for turning on the third main circuit switching power device. PA1 when said logic circuit has generated and outputted the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device, said logic circuit generates and outputs the second switching command signal for turning off the second main circuit switching power device and the fifth switching command signal for turning on the fifth main circuit switching power device, for a time interval from a second timing when the second line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the sixth switching command signal for turning off the sixth main circuit switching power device and the third switching command signal for turning on the third main circuit switching power device, said logic circuit generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and the first switching command signal for turning on the first main circuit switching power device, for a time interval from a second timing when the first line current comparison signal changes to the second level to the next state updating first timing, PA1 wherein, when the first line current comparison signal has the zero level, the second line current comparison signal has the first level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the second and sixth switching command signals for respectively turning off the second and sixth main circuit switching power devices, generates and outputs the third and fifth switching command signals for respectively turning on the third and fifth main circuit switching power devices, generates and outputs either one of the first or fourth switching command signal for turning off the first or fourth main circuit switching power device, and generates and outputs the remaining one switching command signal for turning on the remaining one main circuit switching power device, PA1 when said logic circuit has generated and outputted the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, said logic circuit generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, for a time interval from a second timing when the third line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the fourth switching command signal for turning off the fourth main circuit switching power device and thefirst switching command signal for turning on the first main circuit switching power device, said logic circuit generates and outputs the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, for a time interval from a second timing when the second line current comparison signal changes to the second level to the next state updating first timing, PA1 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the zero level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the third and fourth switching command signals for respectively turning off the third and fourth main circuit switching power devices, generates and outputs the first and sixth switching command signals for respectively turning on the first and sixth main circuit switching power devices, generates and outputs either one of the second or fifth switching command signal for turning off the second or fifth main circuit switching power device, and generates and outputs the remaining one switching command signal for turning on the remaining one main circuit switching power device, PA1 when said logic circuit has generated and outputted the second switching command signal for turning off the second main circuit switching power device and the fifth switching command signal for turning on the fifth main circuit switching power device, said logic circuit generates and outputs the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, for a time interval from a second timing when the first line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, said logic circuit generates and outputs the sixth switching command signal for turning off the sixth main circuit switching power device and the third switching command signal for turning on the third main circuit switching power device, for a time interval from a second timing when the third line current comparison signal changes to the second level to the next state updating first timing, PA1 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the first level and the third line current comparison signal has the zero level at the state updating first timing, said logic circuit generates and outputs the second and fourth switching command signals for respectively turning off the second and fourth main circuit switching power devices, generates and outputs the first and fifth switching command signals for respectively turning on the first and fifth main circuit switching power devices, generates and outputs either one of the third or sixth switching command signal for turning off the third or sixth main circuit switching power device, and generates and outputs the remaining one switching command signal for turning on the remaining one main circuit switching power device, PA1 when said logic circuit has generated and outputted the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device, said logic circuit generates and outputs the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, for a time interval from a second timing when the first line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the sixth switching command signal for turning off the sixth main circuit switching power device and the third switching command signal for turning on the third main circuit switching power device, said logic circuit generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, for a time interval from a second timing when the second line current comparison signal changes to the second level to the next state updating first timing, PA1 wherein, when the first line current comparison signal has the zero level, the second line current comparison signal has the second level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the third and fifth switching command signals for respectively turning off the third and fifth main circuit switching power devices, generates and outputs the second and sixth switching command signals for respectively turning on the second and sixth main circuit switching power devices, generates and outputs either one of the first or fourth switching command signal for turning off the first or fourth main circuit switching power device, and generates and outputs the remaining one switching command signal for turning on the remaining one main circuit switching power device, PA1 when said logic circuit has generated and outputted the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, said logic circuit generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, for a time interval from a second timing when the second line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the fourth switching command signal for turning off the fourth main circuit switching power device and the first switching command signal for turning on the first main circuit switching power device, said logic circuit generates and outputs the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device, for a time interval from a second timing when the third line current comparison signal changes to the second level to the next state updating first timing, and PA1 wherein, when the first line current comparison signal has the first level, the second line current comparison signal has the zero level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the first and sixth switching command signals for respectively turning off the first and sixth main circuit switching power devices, generates and outputs the third and fourth switching command signals for respectively turning on the third and fourth main circuit switching power devices, generates and outputs either one of the second or fifth switching command signal for turning off the second or fifth main circuit switching power device, and generates and outputs the remaining one switching command signal for turning on the remaining one main circuit switching power device, PA1 when said logic circuit has generated and outputted the second switching command signal for turning off the second main circuit switching power device and the fifth switching command signal for turning on the fifth main circuit switching power device, said logic circuit generates and outputs the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device, for a time interval from a second timing when the third line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, said logic circuit generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and the first switching command signal for turning on the first main circuit switching power device, for a time interval from a second timing when the first line current comparison signal changes to the second level to the next state updating first timing. PA1 when said logic circuit has generated and outputted the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device, and further generates and outputs the second switching command signal for turning off the second main circuit switching power device and the fifth switching command signal for turning on the fifth main circuit switching power device for a time interval from a second timing when the second line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the sixth switching command signal for turning off the sixth main circuit switching power device and the third switching command signal for turning on the third main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the sixth switching command signal for turning off the sixth main circuit switching power device and the third switching command signal for turning on the third main circuit switching power device, and further generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and the first switching command signal for turning on the first main circuit switching power device for a time interval from a second timing when the first line current comparison signal changes to the second level to the next state updating first timing, PA1 wherein, when the first line current comparison signal has the zero level, the second line current comparison signal has the first level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the second and sixth switching command signals for respectively turning off the second and sixth main circuit switching power devices, and further generates and outputs the third and fifth switching command signals for respectively turning on the third and fifth main circuit switching power devices, PA1 when said logic circuit has generated and outputted the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, and further generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, for a time interval from a second timing when the third line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the fourth switching command signal for turning off the fourth main circuit switching power device and the first switching command signal for turning on the first main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and the first switching command signal for turning on the first main circuit switching power device, and further generates and outputs the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, for a time interval from a second timing when the second line current comparison signal changes to the second level to the next state updating first timing, PA1 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the zero level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the third and fourth switching command signals for respectively turning off the third and fourth main circuit switching power devices, and further generates and outputs the first and sixth switching command signals for respectively turning on the first and sixth main circuit switching power devices, PA1 when said logic circuit has generated and outputted the second switching command signal for turning off the second main circuit switching power device and the fifth switching command signal for turning on the fifth main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the second switching command signal for turning off the second main circuit switching power device and the fifth switching command signal for turning on the fifth main circuit switching power device, and further generates and outputs the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, for a time interval from a second timing when the first line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, and further generates and outputs the sixth switching command signal for turning off the sixth main circuit switching power device and the third switching command signal for turning on the third main circuit switching power device, for a time interval from a second timing when the third line current comparison signal changes to the second level to the next state updating first timing, PA1 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the first level and the third line current comparison signal has the zero level at the state updating first timing, said logic circuit generates and outputs the second and fourth switching command signals for respectively turning off the second and fourth main circuit switching power devices, and further generates and outputs the first and fifth switching command signals for respectively turning on the first and fifth main circuit switching power devices, PA1 when said logic circuit has generated and outputted the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device, and further generates and outputs the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, for a time interval from a second timing when the first line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the sixth switching command signal for turning off the sixth main circuit switching power device and the third switching command signal for turning on the third main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the sixth switching command signal for turning off the sixth main circuit switching power device and the third switching command signal for turning on the third main circuit switching power device and further generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, for a time interval from a second timing when the second line current comparison signal changes to the second level to the next state updating first timing, PA1 wherein, when the first line current comparison signal has the zero level, the second line current comparison signal has the second level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the third and fifth switching command signals for respectively turning off the third and fifth main circuit switching power devices, and further generates and outputs the second and sixth switching command signals for respectively turning on the second and sixth main circuit switching power devices, PA1 when said logic circuit has generated and outputted the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, and further generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, for a time interval from a second timing when the second line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the fourth switching command signal for turning off the fourth main circuit switching power device and the first switching command signal for turning on the first main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and the first switching command signal for turning on the first main circuit switching power device, and further generates and outputs the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device, for a time interval from a second timing when the third line current comparison signal changes to the second level to the next state updating first timing, and PA1 wherein, when the first line current comparison signal has the first level, the second line current comparison signal has the zero level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the first and sixth switching command signals for respectively turning off the first and sixth main circuit switching power devices, and further generates and outputs the third and fourth switching command signals for respectively turning on the third and fourth main circuit switching power devices, PA1 when said logic circuit has generated and outputted the second switching command signal for turning off the second main circuit switching power device and the fifth switching command signal for turning on the fifth main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the second switching command signal for turning off the second main circuit switching power device and the fifth switching command signal for turning on the fifth main circuit switching power device, and further generates and outputs the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device, for a time interval from a second timing when the third line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, and further generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and the first switching command signal for turning on the first main circuit switching power device, for a time interval from a second timing when the first line current comparison signal changes to the second level to the next state updating first timing.
(b-1) a first main circuit switching power device Q1 which is connected to a positive electrode of the main circuit DC power source 3 and supplies a first line current IU to the three-phase motor 1; PA2 (b-2) a second main circuit switching power device Q2 which is connected to the positive electrode of the main circuit DC power source 3 and supplies a second line current IV to the three-phase motor 1; PA2 (b-3) a third main circuit switching power device Q3 which is connected to the positive electrode of the main circuit DC power source 3 and supplies a third line current IW to the three-phase motor 1; PA2 (b-4) a fourth main circuit switching power device Q4 which is connected to a negative electrode of the main circuit DC power source 3 and supplies the first line current IU to the three-phase motor 1; PA2 (b-5) a fifth main circuit switching power device Q5 which is connected to the negative electrode of the main circuit DC power source 3 and supplies the second line current IV to the three-phase motor 1; PA2 (b-6) a sixth main circuit switching power device Q6 which is connected to the negative electrode of the main circuit DC power source 3 and supplies the third line current IV to the three-phase motor 1; and PA2 (b-7) six reflux diodes each connected in parallel between the collector and the emitter of each of the main circuit switching power devices, and wherein PA2 the main circuit power device circuit 2 operates to turn on either the first main circuit switching power device Q1 or the fourth main circuit switching power device Q4 in accordance with the first switching command signal PU, turn on either the second main circuit switching power device Q2 or the fifth main circuit switching power device Q5 in accordance with the second switching command signal PV, and turn on either the third main circuit switching power device Q3 or the sixth main circuit switching power device Q6 in accordance with the third switching command signal PW. PA2 a first main circuit switching power device which is connected to a positive electrode of the main circuit DC power source and supplies a first line current to the three-phase motor; PA2 a second main circuit switching power device which is connected to the positive electrode of the main circuit DC power source and supplies a second line current to the three-phase motor; PA2 a third main circuit switching power device which is connected to the positive electrode of the main circuit DC power source and supplies a third line current to the three-phase motor; PA2 a fourth main circuit switching power device which is connected to a negative electrode of the main circuit DC power source and supplies the first line current to the three-phase motor; PA2 a fifth main circuit switching power device which is connected to the negative electrode of the main circuit DC power source and supplies the second line current to the three-phase motor; PA2 a sixth main circuit switching power device which is connected to the negative electrode of the main circuit DC power source and supplies the third line current to the three-phase motor; and PA2 six reflux diodes respectively connected in parallel with said first, second, third, fourth, fifth and sixth main circuit switching power devices; PA2 a logic circuit for receiving the first line current comparison signal, the second line current comparison signal and the third line current comparison signal, and generating first, second, third, fourth, fifth and sixth switching command signals for said first, second, third, fourth, fifth and sixth main circuit switching power devices; and PA2 timing generating means for giving a periodical state updating first timing to said logic circuit, PA2 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the first level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the second, third and fourth switching command signals for respectively turning off the second, third and fourth main circuit switching power devices, and further generates and outputs the first, fifth and sixth switching command signals for respectively turning on the first, fifth and sixth main circuit switching power devices, PA2 for a time interval from a second timing when the second line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and further generates and outputs the second switching command signal for turning on the second main circuit switching power device, and for a time interval from a second timing when the third line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the sixth switching command signal for turning off the sixth main circuit switching power device and further generates and outputs the third switching command signal for turning on the third main circuit switching power device, PA2 wherein, when the first line current comparison signal has the first level, the second line current comparison signal has the second level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the first, third and fifth switching command signals for respectively turning off the first, third and fifth main circuit switching power devices, and further generates and outputs the second, fourth and sixth switching command signals for respectively turning on the second, fourth and sixth main circuit switching power devices, PA2 for a time interval from a second timing when the first line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and further generates and outputs the first switching command signal for turning on the first main circuit switching power device, and for a time interval from a second timing when the third line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the sixth switching command signal for turning off the sixth main circuit switching power device and further generates and outputs the third switching command signal for turning on the third main circuit switching power device, PA2 wherein, when the first line current comparison signal has the first level, the second line current comparison signal has the first level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the first, second and sixth switching command signals for respectively turning off the first, second and sixth main circuit switching power devices, and further generates and outputs the third, fourth and fifth switching command signals for respectively turning on the third, fourth and fifth main circuit switching power devices, PA2 for a time interval from a second timing when the first line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and further generates and outputs the first switching command signal for turning on the first main circuit switching power device, and for a time interval from a second timing when the second line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and further generates and outputs the second switching command signal for turning on the second main circuit switching power device, PA2 wherein, when the first line current comparison signal has the first level, the second line current comparison signal has the second level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the first, fifth and sixth switching command signals for respectively turning off the first, fifth and sixth main circuit switching power devices, and further generates and outputs the second, third and fourth switching command signals for respectively turning on the second, third and fourth main circuit switching power devices, PA2 for a time interval from a second timing when the second line current comparison signal changes from the second level to the first level to the next state updating first timing, said logic circuit generates and outputs the second switching command signal for turning off the second main circuit switching power device and further generates and outputs the fifth switching command signal for turning on the fifth main circuit switching power device, and for a time interval from a second timing when the third line current comparison signal changes from the second level to the first level to the next state updating first timing, said logic circuit generates and outputs the third switching command signal for turning off the third main circuit switching power device and further generates and outputs the sixth switching command signal for turning on the sixth main circuit switching power device, PA2 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the first level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the second, fourth and sixth switching command signals for respectively turning off the second, fourth and sixth main circuit switching power devices, and further generates and outputs the first, third and fifth switching command signals for respectively turning on the first, third and fifth main circuit switching power devices, PA2 for a time interval from a second timing when the first line current comparison signal changes from the second level to the first level to the next state updating first timing, said logic circuit generates and outputs the first switching command signal for turning off the first main circuit switching power device and further generates and outputs the fourth switching command signal for turning on the fourth main circuit switching power device, and for a time interval from a second timing when the third line current comparison signal changes from the second level to the first level to the next state updating first timing, said logic circuit generates and outputs the third switching command signal for turning off the third main circuit switching power device and further generates and outputs the sixth switching command signal for turning on the sixth main circuit switching power device, and PA2 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the second level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the third, fourth and fifth switching command signals for respectively turning off the third, fourth and fifth main circuit switching power devices, and further generates and outputs the first, second and sixth switching command signals for respectively turning on the first, second and sixth main circuit switching power devices, and PA2 for a time interval from a second timing when the first line current comparison signal changes from the second level to the first level to the next state updating first timing, said logic circuit generates and outputs the first switching command signal for turning off the first main circuit switching power device and further generates and outputs the fourth switching command signal for turning on the fourth main circuit switching power device, and for a time interval from a second timing when the second line current comparison signal changes from the second level to the first level to the next state updating first timing, said logic circuit generates and outputs the second switching command signal for turning off the second main circuit switching power device and further generates and outputs the fifth switching command signal for turning on the fifth main circuit switching power device.
In this case, when the first switching command signal PU becomes a High level (referred to as an H-level hereinafter), the first main circuit switching power device Q1 is turned on. On the other hand, when the first switching command signal PU becomes a Low level (referred to as an L-level hereinafter), the fourth main circuit switching power device Q4 is turned on. When the second switching command signal PV becomes the H-level, the second main circuit switching power device Q2 is turned on. On the other hand, when the second switching command signal PV becomes the L-level, the fifth main circuit switching power device Q5 is turned on. When the third switching command signal PW becomes the H-level, the third main circuit switching power device Q3 is turned on. On the other hand, when the third switching command signal PW becomes the L-level, the sixth main circuit switching power device Q6 is turned on.
As above is described the structure and operation of the generic current command type PWM inverter system.
A structure of a prior art current command type PWM inverter will be described below with reference to FIG. 10.
FIG. 10 shows a structure of the prior art current controller 106 of the current command type PWM inverter system shown in FIG. 9.
FIGS. 11A through 11E show an operation of the inverter system shown in FIG. 10.
First of all, the first, second and third line current command signals iTU, iTV and iTW and the first, second and third detected line currents iFU, iFV and iFW are subjected to a subtraction process respectively in subtracters 117, 118 and 119 to obtain the first, second and third line current error signals iEU, iEV and iEW. Then first, second and third current error amplifiers 120, 121 and 122 receive the first, second and third line current error signals iEU, iEV and iEW, respectively, and then, output amplified voltage command signals VU, VV and VW, respectively. Each of the current error amplifiers 120, 121 and 122 is generally implemented by a proportion and integration type amplifier as shown in FIG. 12, and a gain characteristic thereof can be represented by the Equation (1): EQU G=R2.times.(R3.times.C1.times.S)/R1.times.{(R2+R3).times.C1.times.S+1}!(1) .
The reference numeral 139 denotes a three-phase PWM signal generator comprised of first, second and third comparators 123, 124 and 125 and a triangular wave generator 126. The first, second and third comparators 123, 124 and 125 compare a triangular wave signal SC outputted from the triangular wave generator 126 with the respective voltage command signals VU, VV and VW, respectively, and then, output the first, second and third switching command signals PU, PV and PW, respectively.
In the present case, each of the first, second and third comparators 123, 124 and 125 outputs the H-level when each of the voltage command signals VU, VV and VW is greater than the triangular wave signal SC, while each of the first, second and third comparators 123, 124 and 125 outputs the L-level when each of the voltage command signals VU, W and VW is smaller than the triangular wave signal SC.
FIGS. 11A through 11E show an operation of the current controller 106 shown in FIG. 10, when the first, second and third line current command signals iTU, iTV and iTW are three-phase sine waves, respectively.
Considering the gains of the current error amplifiers 120, 121 and 122 shown in FIGS. 10 and 11A through 11E, it can be understood that each line current error can be reduced by increasing the gains of the current error amplifiers 120, 121 and 122 as a consequence of approach of the detected line currents to the respective line current command signals, and the responsibility of the detected line currents to the respective line current command signals is improved.
However, according to the structure of the above-mentioned prior art, owing to a phase delay due to an electric time constant of the three-phase motor, phase delays of the current error amplifiers, a waste time delay of the three-phase PWM signal generator and the like, an oscillation phenomenon will occur when the current error amplifier gain is made too great. Therefore, the gain of each of the current error amplifiers is generally set to a value which is as great as possible and falls within a range in which no oscillation occurs. The gain of each of the current error amplifiers is determined in the designing stage by examining a loop transfer function of the current control loop from the characteristics of the three-phase motor, the motor current detector circuit, the current controller and the main circuit power controller. In the present case, considering the manufacturing-dependent variation of the characteristics and temperature characteristics, it is required to reduce the gain to a level at which no oscillation phenomenon occurs at worst. The work for determining the gain requires much labor of the operators engaging in the designing, and even a current command type PWM inverter having the same structure requires gain adjustment depending on different motors to which the inverter is to be connected, incurring such a problem that much labor is required for the control of the manufacturing process.
Furthermore, when the specifications of the three-phase motor to be connected to the current command type PWM inverter have not yet determined in the designing stage (e.g., in the case of a general use inverter, a general use AC servo driver or the like), it is required to adjust the gain in accordance with the specifications of the three-phase motor upon determining and installing the three-phase motor to which the inverter is to be connected, and there is such a problem that this gain adjustment work is a bottleneck.
Furthermore, the offset and drift of the triangular wave generator and the current error amplifiers themselves deteriorate the current control error and narrow the dynamic ranges of the amplified error signals. Therefore, an operational amplifier having a small offset and drift is required as a component of them, and depending on the cases, offset adjusting work is required in the manufacturing stage, incurring the problem of cost increase.
FIG. 10 shows a prior art example of the current controller 106 implemented by an analog circuit, however, there exists a current controller implementing a similar structure by a digital circuit such as a microcomputer which subjects the first, second and third detected line currents iFU, iFV and iFW to an analog to digital conversion process by means of an A/D converter. In such a case, the gain of the current error amplifier is required to be determined by examining the loop transfer function of the current control loop from the characteristics of the three-phase motor, the motor current detector circuit, the current controller and the main circuit power controller, and their problems are the same as those of the current controller implemented by the analog circuit.
Furthermore, when the current error amplifier is implemented by a digital circuit such as a microcomputer or the like, the offset and drift of the current error amplifier itself can be eliminated because they are achieved by digital calculation. However, as the calculation processing time increases, the phase delay increases and the circuit tends to oscillate. This consequently means that the gain cannot be increased unless the processing time is reduced, and therefore, a microcomputer having a very high speed calculation processing capability or the like must be used, incurring the problem of cost increase.
Furthermore, the phase delay of the A/D converter for converting the first, second and third detected line currents iFU, iFV and iFW into digital data becomes greater as the time for conversion increases, and the circuit tends to oscillate. This consequently means that the gain cannot be increased unless the conversion time is reduced, and therefore, an A/D converter having a very high speed conversion capability must be used, incurring the problem of cost increase. Furthermore, the offset and drift of the A/D converter consequently deteriorate the current control error and narrow its dynamic range. Therefore, it is required to select an A/D converter having smaller offset and drift, incurring the problem of cost increase.
Furthermore, the three-phase PWM command signal generator implemented by a digital circuit has such problems that the three-phase PWM command signal generator has a complicated structure and costs much as shown in the digital three-phase PWM wave generating apparatus disclosed in the Japanese Patent Laid-Open Publication No. 4-312360.